UPSD3422EB40U6 datasheet(249/300 Pages) STMICROELECTRONICS

249 / 300 page

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csiop PMMR registers. Current consumption of the PLDs is directly related to the

composite frequency of all transitions on PLD inputs, so blocking certain PLD inputs

can significantly lower PLD operating frequency and power consumption (resulting in a

lower frequency on the graphs of Figure 95 on page 265 and Figure 96 on page 266).

Note:

It is recommended to prevent unused inputs from floating on Ports A, B, C, and D by pulling

them up to VDD with a weak external resistor (100KΩ), or by setting the csiop Direction

of unused input pins from drawing excessive current.

The csiop PMMR register definitions are shown in Table 200 through Table 202 on

page 250.

Table 200.

Power management mode register PMMR0 (address = csiop + offset

B0h)(1)

All the bits of this register are cleared to zero following power-up. Subsequent Reset (RST) pulses do not

clear the registers.

Bit 0

Not used, and should be set to zero.

Bit 1

APD Enable

Automatic Power Down (APD) counter is disabled.

APD counter is enabled

Bit 2

Not used, and should be set to zero.

Bit 3

PLD Turbo

Disable

0 =

PLD Turbo mode is on

1 =

off

PLD Turbo mode is off, saving power.

Bit 4

Blocking Bit,

CLKIN to

PLDs(2)

Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.

0 =

CLKIN (pin PD1) to the PLD Input Bus is not blocked. Every transition of

CLKIN powers-up the PLDs.

1 =

off

CLKIN input to PLD Input Bus is blocked, saving power. But CLKIN still

goes to APD counter.

Bit 5

Blocking Bit,

CLKIN to

OMCs

Only(2)

0 =

CLKIN input is not blocked from reaching all OMCs’ common clock

inputs.

1 =

off

CLKIN input to common clock of all OMCs is blocked, saving power. But

CLKIN still goes to APD counter and all PLD logic besides the common

clock input on OMCs.

Bit 6

Not used, and should be set to zero.

Bit 7

Not used, and should be set to zero.

Table 201.

Power management mode register PMMR2 (address = csiop + offset

B4h)(1)

Bit 0

Not used, and should be set to zero.

Bit 1

Not used, and should be set to zero.

Bit 2

Blocking Bit,

WR to

PLDs(2)

0 =

8032 WR input to the PLD Input Bus is not blocked.

1 =

off

8032 WR input to PLD Input Bus is blocked, saving power.

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UPSD3422EB40U6 데이터시트(PDF) 249 Page - STMicroelectronics

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