UPSD3422EB40U6 datasheet(284/300 Pages) STMICROELECTRONICS

284 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

DC and AC parameters

UPSD3422, UPSD3433, UPSD3434, UPSD3454

284/300

Figure 105. Peripheral I/O READ timing

PLD program / erase cycles

1 000

cycles

tWHWLO

Sector erase timeout

100

µs

tQ7VQV

DQ7 valid to output (DQ7-DQ0) valid (data

polling)(3)

Programmed to all zero before erase.

Typical after 100 000 Write/Erase cycles is 5 seconds.

The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

Table 229.

Port A peripheral data mode READ timing (5 V PSD module)

Symbol

Parameter

Conditions

Min

Max

Turbo off

Unit

tAVQV–PA

Address valid to data valid

(1)

Any input used to select Port A data peripheral mode.

+ 10

tSLQV–PA

CSI valid to data valid

+ 10

tRLQV–PA

RD to data valid

(2)

Data is already stable on Port A.

tDVQV–PA

Data in to data out valid

tRHQZ–PA RD to data High-Z

Table 228.

Program, WRITE and erase times (5 V, 3 V PSD modules) (continued)

Symbol

Parameter

Min.

Typ.

Max.

Unit

tRLQV (PA)

tDVQV (PA)

tRHQZ (PA)

tSLQV (PA)

tAVQV (PA)

ADDRESS

DATA VALID

ALE

A /D BUS

DATA ON PORT A

CSI

AI06610

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422EB40U6 데이터시트(PDF) 284 Page - STMicroelectronics

UPSD3422EB40U6 데이터시트(HTML) 284 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL