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74HC 데이터시트(PDF) 5 Page - NXP Semiconductors

부품명 74HC
상세설명  Dual JK flip-flop with set and reset; positive-edge trigger
PDF  9 Pages
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HC 데이터시트(HTML) 5 Page - NXP Semiconductors

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1997 Nov 25
5
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
74HC/HCT109
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
SYMBOL
PARAMETER
Tamb (°C)
TEST CONDITIONS
74HC
UNIT
VCC
(V)
WAVEFORMS
+25
−40 to +85
−40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
nCP to nQ, nQ
50
18
14
175
35
30
220
44
37
265
53
45
ns
2.0
4.5
6.0
Fig.6
tPLH
propagation delay
nSD to nQ
30
11
9
120
24
20
150
30
26
180
36
31
ns
2.0
4.5
6.0
Fig.7
tPHL
propagation delay
nSD to nQ
41
15
12
155
31
26
195
39
33
235
47
40
ns
2.0
4.5
6.0
Fig.7
tPHL
propagation delay
nRD to nQ
41
15
12
185
37
31
230
46
39
280
56
48
ns
2.0
4.5
6.0
Fig.7
tPLH
propagation delay
nRD to nQ
39
14
11
170
34
29
215
43
37
255
51
43
ns
2.0
4.5
6.0
Fig.7
tTHL/ tTLH
output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Fig.6
tW
clock pulse width
HIGH or LOW
80
16
14
19
7
6
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.6
tW
set or reset pulse
width HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
trem
removal time
nSD,nRD to nCP
70
14
12
19
7
6
90
18
15
105
21
18
ns
2.0
4.5
6.0
Fig.7
tsu
set-up time
nJ, nK to nCP
70
14
12
17
6
5
90
18
15
105
21
18
ns
2.0
4.5
6.0
Fig.6
th
hold time
nJ, nK to nCP
5
5
5
0
0
0
5
5
5
5
5
5
ns
2.0
4.5
6.0
Fig.6
fmax
maximum clock
pulse frequency
6.0
30
35
22
68
81
5.0
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.6



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