| 전자부품 데이터시트 검색엔진 |
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L9305 데이터시트(PDF) 48 Page - STMicroelectronics |
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L9305 데이터시트(HTML) 48 Page - STMicroelectronics |
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48 / 107 page ![]() Figure 23. SPI frame after Power On Reset Frame #0 Add_#0 Data[Add_#0] IC Registers Data_#0 = 0xYYYY R 0 0 crc 0 0 0 crc Data_fdbk = 0x0000 Add_fdbk = 0x00 Frame #n+1 Add_#1 Data_#1 = 0xYYYY RW 0 0 crc 0 0 0 crc Data_#0 Add_#0 GADG2709181452PS Upon reading a register with Clear on Read fields, the related bits will be cleared only when data has been completely moved on the next SPI access as shown in Figure 24. Figure 24. Clear on Read SPI sequence Frame #n Add_#n Data[Add_#n] [cleared] IC Registers Data_#n = 0x0000 R 0 0 crc 0 0 0 crc Data_#n-1 Add_#n-1 Frame #n+1 Add_#n+1 Data_#n+1 = 0xYYYY RW 0 0 crc 0 0 0 crc Data_#n Add_#n GADG2709181454PS Data[Add_#n] [uncleared] IC Registers Upon register write, data is updated after the frame is completely received and no error has been detected (CRC, frame sequence, frame length). On the next SPI access, MISO data field will contain updated data content from the written register as shown in Figure 25. Figure 25. SPI write sequence Frame #n Add_#n Data[Add_#n] IC Registers Data__#n = 0xABCD W 0 0 crc 0 0 0 crc Data_#n-1 Add_#n-1 Frame #n+1 Add_#n+1 Data_#n+1 = 0xYYYY RW 0 0 crc 0 0 0 crc Data_#n = ABCD Add_#n GADG2709181455PS The SPI interface is supplied by VDDIO pin and consists of the following pins and definitions: L9305 SPI protocol DS12774 - Rev 8 page 48/107 |
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