5.2

Read operations

Read operations are performed independently of the state of the write control (WC) signal.

After the successful completion of a read operation, the device internal address counter is incremented by one, to

point to the next byte address.

For the read instructions, after each byte read (data out), the device waits for an acknowledgement (data in)

during the 9th bit time. If the bus master does not acknowledge during this 9th time, the device terminates the data

transfer and switches to its standby mode.

Figure 9. Read mode sequences

Dev select *

Byte address

Dev select

Data out 1

Data out N

Current Address Read

Dev select

Data out

Random Address Read

Dev select *

Data out

Sequential Current Read

Data out N

Dev select *

Byte address

Sequential Random Read

Dev select *

Data out 1

ACK

R/W

NO ACK

ACK

R/W

ACK

ACK

R/W

ACK

ACK

ACK

NO ACK

R/W

NO ACK

ACK

ACK

R/W

ACK

ACK

R/W

ACK

NO ACK

5.2.1

Random address read

A dummy write is first performed to load the address into this address counter (as shown in Figure 9) but without

sending a stop condition. Then, the bus master sends another start condition, and repeats the device select code,

with the R/W bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus

master must not acknowledge the byte, and terminates the transfer with a stop condition.

M24C16-W M24C16-R M24C16-F

Read operations

DS9194 - Rev 11

page 12/40