STE2004 datasheet(7/66 Pages) STMICROELECTRONICS

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STE2004

Figure 4. Master Slave Logic Connection with frame Synchronization

Figure 5. Master Slave Logic Connection without frame Synchronization

3.5 Bias Levels

To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated.

The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are

established to be (Fig. 6):

Figure 6. Bias level Generator

thus providing an 1/(n+4) ratio, with n calculated from:

For m = 65, n = 5 and an 1/9 ratio is set.

For m = 49, n =4 and an 1/8 ratio is set.

The STE2004 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:

OSCOUT

LR0219

STE2004

VDD1AUX

STE2004

FROUT

OSCIN

FRIN

OSCIN FRIN

OSCOUT

FROUT

OSCOUT

LR0220

STE2004

VDD1AUX

STE2004

FROUT

OSCIN FRIN

OSCOUT

FROUT

VDD1AUX

OSCIN

FRIN

LCD

------------- V

LCD ,

------------- V

LCD ,

------------- V

LCD ,

------------- V

LCD ,VSS

VLCD

VSS

·VLCD

n + 3

n + 4

n + 2

n + 4

D00IN1150

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