MCP2518FD datasheet(72/96 Pages) MICROCHIP

72 / 96 page

MCP2518FD

DS20000000A-page 72

 2019 Microchip Technology Inc.

4.3.5

MESSAGE MEMORY READ

WITH CRC – READ_CRC

Figure 4-11 illustrates the READ_CRC instruction,

while accessing RAM. The instruction starts with nCS

going low. The Command (C<3:0> = 0b1011), is fol-

lowed by the Address (A<11:0>), and the number of

data Words (N<7:0>). Afterwards, the data byte from

address A (DB[A]) is shifted out, followed by data byte

from address A+1 (DB[A+1]). Next the CRC

(CRC<15:0>) is shifted out. The instruction ends when

nCS goes high.

Writes and Reads must be word-aligned. The lower

two bits of the address are always assumed to be 0. It

is not possible to do unaligned reads/writes.

Read commands should always read a multiple of 4

data bytes. A word is internally read from RAM after

the “N” field, and after every fourth data byte read on

the SPI. In case nCS goes high before a multiple of 4

data bytes are read on SDO, the incomplete read

should be discarded by the microcontroller.

The CRC is provided to the microcontroller. The micro-

controller checks the CRC. No interrupt is generated

on CRC mismatch during a READ_CRC command

inside the MCP2518FD device.

If nCS goes high before the last byte of the CRC is

shifted out, a CRC Form Error interrupt is generated:

CRC.FERRIF.

4.3.6

MESSAGE MEMORY WRITE

WITH CRC – WRITE_CRC

Figure 4-12 illustrates the WRITE instruction access-

ing the RAM. The instruction starts with nCS going

low. The Command (C<3:0> = 0b1010), is followed by

the Address (A<11:0>), and the number of data Words

(N<7:0>). Afterwards, the data byte is shifted into

address A (DB[A]), next into address A+1 (DB[A+1]).

Next the CRC (CRC<15:0>) is shifted in. The instruc-

tion ends when nCS goes high.

Write commands must always write a multiple of 4

data bytes. After every fourth data byte, with the falling

edge on SCK, the RAM gets written. In case nCS goes

high before a multiple of 4 data bytes is received on

SDI, the data of the incomplete Word will not be

written to RAM.

The CRC is checked at the end of the write access. In

case of a CRC mismatch, a CRC interrupt is

generated: CRC.CRCERRIF.

If nCS goes high before the last byte of the CRC is

shifted in, a CRC interrupt is generated: CRC.FERRIF.

FIGURE 4-11:

MESSAGE MEMORY READ WITH CRC INSTRUCTION

FIGURE 4-12:

MESSAGE MEMORY WRITE WITH CRC INSTRUCTION

4.3.7

MESSAGE MEMORY WRITE SAFE

WITH CRC – WRITE_SAFE

This instruction ensures that only correct data is

written to RAM.

Figure 4-10 illustrates the WRITE_SAFE instruction,

while accessing RAM. The instruction starts with nCS

going low. The Command (C<3:0> = 0b1100), is

followed by the Address (A<11:0>). Afterwards, the

data byte is shifted into address A (DB[A]), next into

address A+1 (DB[A+1]), A+2 (DB[A+2]), and A+3

(DB[A+3]). Next the CRC (CRC<15:0>) is shifted in.

The instruction ends when nCS goes high.

The data word is only written to RAM after the CRC is

checked and if it matches.

If the CRC mismatches, the data word is not written to

RAM and a CRC Error interrupt is generated:

CRC.CRCERRIF.

If nCS goes high before the last byte of the CRC is

shifted in, a CRC interrupt is generated: CRC.FERRIF.

FIGURE 4-13:

MESSAGE MEMORY WRITE SAFE WITH CRC INSTRUCTION

DW[A]

DB[A]

DB[A+1]

DB[A+3]

DB[A+2]

0b1011

A<11:0>

nCS Low

nCS High

N<7:0>

CRC<15:8>

CRC<7:0>

DW[A]

DB[A]

DB[A+1]

DB[A+3]

DB[A+2]

0b1010

A<11:0>

nCS Low

nCS High

N<7:0>

CRC<15:8>

CRC<7:0>

DW[A]

DB[A]

DB[A+1]

DB[A+3]

DB[A+2]

0b1100

A<11:0>

nCS Low

nCS High

CRC<15:8>

CRC<7:0>

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