DFE252012P-2R2M datasheet(14/44 Pages) MICROCHIP

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MCP16501

DS20006388A-page 14

 2020 Microchip Technology Inc.

3.0

PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Number

Pin Name

Description

OUT1

Output Sensing for Buck Channel 1. Connect to the regulation point for VOUT1.

nRSTO

Active-Low, Open-Drain Reset Output.

PWRHLD Power Hold Input. Typically asserted as high by the MPU to maintain power after the

initial start-up is triggered by nSTRT. PWRHLD is to be asserted as low by the MPU

to initiate a PMIC shutdown sequence.

LPM

Low-Power Mode Input Pin. In combination with PWRHLD, this pin defines the

power mode status of the MCP16501.

nSTRTO

Active-Low, Open-Drain Start Event Output. nSTRTO is asserted low whenever

nSTRT is low.

OUT2

Output Sensing for Buck Channel 2. Connect to the regulation point for VOUT2.

PVIN2

Power Input Voltage of Buck Channel 2. Connect a ceramic capacitor from PVIN2 to

the PGND2 pin to localize pulsed current loops and decouple switching noise.

SW2

Switch Node of Buck Channel 2. Internal power MOSFET switches and external

inductor connection.

PGND2

Power Ground of Buck Channel 2.

PGND3

Power Ground of Buck Channel 3.

SW3

Switch Node of Buck Channel 3. Internal power MOSFET switches and external

inductor connection.

PVIN3

Power Input Voltage of Buck Channel 3. Connect a ceramic capacitor from PVIN3 to

the PGND3 pin to localize pulsed current loops and decouple switching noise.

OUT3

Output Sensing for Buck Channel 3. Connect to the regulation point for VOUT3.

nSTRT

Start Event Input. Drive nSTRT to low to initiate a start-up sequence. nSTRT is

pulled up internally. A capacitor can be connected to nSTRT to automatically initiate

a power-up sequence when the main supply rises.

SELV3

Buck Channel 3 Output Voltage Selection Pin. Three-state input.

SGND

Signal Ground. Connect to reference ground plane.

VIN

Input voltage for the LDO and for the analog control circuitry. Decouple VIN to SGND

with a 2.2uF (minimum) ceramic capacitor.

LOUT

LDO Output. Decouple LOUT to ground with a 2.2 µF (minimum) ceramic capacitor.

LFB

LDO FB pin. Connect to an external resistor divider to LOUT for output voltage

adjustment.

SELV2

Buck Channel 2 Output Voltage Selection Pin. Three-state input.

LEN

LDO Enable input.

PGND1

Power Ground of Buck Channel 1.

SW1

Switch Node of Buck Channel 1. Internal power MOSFET switches and external

inductor connection.

PVIN1

Power Input Voltage of Buck Channel 1. Connect a ceramic capacitor from PVIN1 to

the PGND1 pin, to localize pulsed current loops and decouple switching noise.

Exposed Pad. Connect to ground plane with vias to ensure good thermal properties.

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