HC705JB2GRSSLASHH datasheet(66/128 Pages) NXP

66 / 128 page

GENERAL RELEASE SPECIFICATION

August 28, 1998

PROGRAMMABLE TIMER

MC68HC705JB2

9-8

REV 1.1

Disable interrupts by setting the I bit in the condition code register.

Write to the OCRH. Compares are now inhibited until OCRL is written.

Read the TSR to arm the OCF for clearing.

Enable the output compare registers by writing to the OCRL. This also

clears the OCF ﬂag bit in the TSR.

Enable interrupts by clearing the I bit in the condition code register.

A software example of this procedure is shown below.

9.5

TIMER CONTROL REGISTER (TCR)

The timer control register is shown in Figure 9-10 performs the following

functions:

•

Enables input capture interrupts

•

Enables output compare interrupts

•

Enables timer overﬂow interrupts

•

Control the active edge polarity of the TCAP signal on pin PB0/TCAP

Reset clears all the bits in the TCR with the exception of the IEDG bit which is

unaffected.

ICIE - INPUT CAPTURE INTERRUPT ENABLE

This read/write bit enables interrupts caused by an active signal on the PB0/

TCAP pin. Reset clears the ICIE bit.

1 =

Input capture interrupts enabled.

0 =

Input capture interrupts disabled.

...

SEI

...

STA

LDA

STX

...

CLI

OCRH

TSR

OCRL

DISABLE INTERRUPTS

.....

INHIBIT OUTPUT COMPARE

ARM OCF FLAG FOR CLEARING

READY FOR NEXT COMPARE, OCF CLEARED

.....

ENABLE INTERRUPTS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TCR

ICIE

OCIE

TOIE

000

IEDG

$0012

reset:

000000

Unaffected

Figure 9-10. Timer Control Register (TCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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