HC705JJ7GRSSLASHD datasheet(71/230 Pages) NXP

부품명	HC705JJ7GRS/D

상세설명	Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)

PDF	230 Pages

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Operating Modes

Low-Power Modes

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Operating Modes

Therefore, the lowest power is consumed when OM1 is cleared. The

state with both OM1 and OM2 set is provided so that the EPO can be

started up and allowed to stabilize while the LPO still clocks the MCU.

NOTE:

When switching from LPO to EPO, the user must be careful to ensure

that the EPO has been enabled and powered up long enough to stabilize

before shifting clock sources.

IRQF — External Interrupt Request Flag

The IRQF flag is a clearable, read-only bit that is set when an external

interrupt request is pending. Refer to Section 4. Interrupts for more

details.

IRQR — Interrupt Request Reset

This write-only bit clears the IRQF flag bit and prevents redundant

execution of interrupt routines. Refer to Section 4. Interrupts for

more details.

6.4 Low-Power Modes

Four modes of operation reduce power consumption:

•

Stop mode

•

Wait mode

•

Halt mode

•

Data-retention mode

Figure 6-2 shows the sequence of events in stop, wait, and halt modes.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D 데이터시트(PDF) 71 Page - NXP Semiconductors