HC705JJ7GRSSLASHD datasheet(108/230 Pages) NXP

108 / 230 page

Analog Subsystem

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Analog Subsystem

INV

This is a read/write bit that controls the relative polarity of the inherent

input offset voltage of the voltage comparators. This bit allows voltage

comparisons to be made with both polarities and then averaged

together by taking the sum of the two readings and then dividing by 2

(logical shift right).

The polarity of the input offset is reversed by interchanging the

internal voltage comparator inputs while also inverting the comparator

output. This interchange does not alter the action of the voltage

comparator output with respect to its port pins. That is, the output will

only go high if the voltage on the positive input (PB2 pin for

comparator 1 and PB0 pin for comparator 2) is above the voltage on

the respective negative input (PB3 pin for comparator 1 and PB1 pin

for comparator 2). This is shown schematically in Figure 8-4. This bit

is cleared by a reset of the device.

1 = The voltage comparators are internally inverted.

0 = The voltage comparators are not internally inverted.

Figure 8-4. INV Bit Action

NOTE:

The effect of changing the state of the INV bit is to only change the

polarity of the input offset voltage. It does not change the output phase

of the CPF1 or CPF2 flags with respect to the external port pins.

V-

V+

INV = 0

COMP

VIO

RISE

WHEN

V+ > V-

INV = 1

V+

V-

COMP

VIO

RISE

WHEN

V+ > V-

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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