7LVC841APWDH datasheet(6/10 Pages) PHILIPS

6 / 10 page

Philips Semiconductors

Product specification

74LVC841A

10-bit transparent latch with 5-volt tolerant

inputs/outputs (3-State)

1998 Jun 17

AC WAVEFORMS

VM = 1.5 V at VCC ≥ 2.7 V

VM = 0.5 V × VCC at VCC < 2.7 V

VM = 1.5 V at VCC = 3.0 V

VOL and VOH are the typical output voltage drop that occur with the

output load.

VX = VOL + 0.3 V at VCC ≥ 2.7 V

VX = VOL + 0.1 × VCC at VCC < 2.7 V

VY = VOH – 0.3 V at VCC ≥ 2.7 V

VY = VOH – 0.1 × VCC at VCC < 2.7 V

SV01727

Dn Input

Qn Output

tPLH

tPHL

GND

VOL

VOH

Figure 1. Input (Dn) to output (Qn) propagation delays.

SV01729

LE INPUT

GND

VOL

VOH

Qn OUTPUT

t PLH

t PHL

Figure 2. Latch enable input (LE) pulse width, the latch enable

input to output (Qn) propagation delays.

SV01728

outputs

disabled

outputs

enabled

outputs

enabled

tPHZ

tPZH

tPZL

tPLZ

OE INPUT

Qn OUTPUT

LOW-to-OFF

OFF-to-LOW

Qn OUTPUT

HIGH-to-OFF

OFF-to-HIGH

VOL

GND

VOH

VCC

Figure 3. 3-State enable and disable times.

SV01730

Dn INPUT

LE INPUT

GND

tsu

t su

Figure 4. Data set-up and hold times for the

Dn input to LE input.

Note to Figure 4: The shaded areas indicate when the input is

permitted to change for predictable output performance

TEST CIRCUIT

PULSE

GENERATOR

D.U.T.

50pF

2 x VCC

Open

GND

500

Ω

500

Ω

VCC

t 2.7V

VCC

2.7V – 3.6V

2.7V

Test

GND

tPLZ/tPZL

2 x VCC

tPHZ/tPZH

tPLH/tPHL

Open

SY00003

VCC

Figure 5. Load circuitry for switching times.

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