8.11.1

Microcontroller core

The secondary side is controlled by a Cortex M0+ core clocked at FCK/2, with 8kB static RAM and 64kB

programmable flash code memory. The flash is loaded in production with a complete code managing both the

voltage conversion of an active clamp flyback and the protocol for USB-PD PPS.

A dedicated 8kB ROM area is reserved for the boot activity and trimming area.

8.11.1.1

Parameter memory

A section of the flash is dedicated to parameters which can be programmed by the user to tune the power

conversion, set up the application functionality, choose the protocol and the PDOs or APDOs to be used.

8.11.2

SMED

A set of dedicated event driven state machines can generate complex PWMs. The transitions between the states

can be controlled by either timings or external events, or a combination of the two.

The SMED configuration is fully managed by the IC firmware to implement the control modes described in

Section 8.5 .

ST-ONEMP

Secondary side controller

DS13989 - Rev 2

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