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STM32C011F6U6 데이터시트(PDF) 14 Page - STMicroelectronics

부품명 STM32C011F6U6
상세설명  Arm® Cortex®-M0 32-bit MCU, 32 KB Flash, 6 KB RAM,2 x USART, timers, ADC, comm. I/Fs, 2-3.6 V
PDF  94 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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Functional overview
STM32C011x4/x6
14/94
DS13866 Rev 3
Figure 2. Power supply overview
3.7.2
Power supply supervisor
The device has an integrated power-on/power-down (POR/PDR) reset active in all power
modes except Shutdown and ensuring proper operation upon power-on and power-down. It
maintains the device in reset when the supply voltage is below VPOR/PDR threshold, without
the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It
can be enabled and configured through option bytes, by selecting one of four thresholds for
rising VDD and other four for falling VDD.
3.7.3
Voltage regulator
An embedded linear voltage regulator supplies most of the digital circuitry in the device.
In Standby and Shutdown modes, the regulator is powered down and its output set in high-
impedance state, such as to bring its current consumption close to zero.
3.7.4
Low-power modes
By default, the device is in Run mode after system or power reset. It is up to the user to
select one of the low-power modes described below:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
In Stop mode, the device achieves the lowest power consumption while retaining the
SRAM and register contents. All clocks in the VCORE are stopped. The HSE and HSI48
VDDA domain
RTC domain
A/D converter
Standby circuitry
(Wakeup logic,
IWDG)
Voltage regulator
Core
SRAM
Digital
peripherals
LSE 32KHz
RCC BDCR register
RTC
I/O ring
VCORE domain
Temp. sensor
Reset block
HSI48
Flash memory
VDDIO1
VDD domain
VCORE
VSS
VDD
VDDA
VREF+
VSSA
VSS
VDD



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