STM32U535NET3QTR datasheet(78/278 Pages) STMICROELECTRONICS

78 / 278 page

Functional overview

STM32U535xx

78/278

DS14217 Rev 1

•

LIN master synchronous break send capability and LIN slave break detection capability

–

13-bit break generation and 10/11-bit break detection when USART is hardware

configured for LIN

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IrDA SIR encoder decoder supporting 3/16-bit duration for Normal mode

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Smartcard mode

–

Supports the T = 0 and T = 1 asynchronous protocols for smartcards as defined in

the ISO/IEC 7816-3 standard

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0.5 and 1.5 stop bits for Smartcard operation

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Support for Modbus communication

–

Timeout feature

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CR/LF character recognition

3.39.2

Low-power universal asynchronous receiver transmitter (LPUART)

The LPUART supports bidirectional asynchronous serial communication with minimum

power consumption. It also supports half-duplex single-wire communication and modem

operations (CTS/RTS). It allows multiprocessor communication.

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to

9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame

while having an extremely low energy consumption. Higher-speed clock can be used to

reach higher baudrates.

The LPUART interface can be served by the DMA controller.

The LPUART main features are:

•

Full-duplex asynchronous communications

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NRZ standard format (mark/space)

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Programmable baud rate

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From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source

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Higher baud rates can be achieved by using a higher frequency clock source

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Two internal FIFOs to transmit and receive data

Each FIFO can be enabled/disabled by software and come with status flags for

FIFO states.

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Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK

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Programmable data word length (7 or 8 or 9 bits)

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Programmable data order with MSB-first or LSB-first shifting

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Configurable stop bits (1 or 2 stop bits)

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Single-wire half-duplex communications

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Continuous communications using DMA

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Received/transmitted bytes are buffered in reserved SRAM using centralized DMA

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Separate enable bits for transmitter and receiver

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Separate signal polarity control for transmission and reception

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Swappable Tx/Rx pin configuration

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Hardware flow control for modem and RS-485 transceiver

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