전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

STM32U535NET3QTR 데이터시트(PDF) 210 Page - STMicroelectronics

부품명 STM32U535NET3QTR
상세설명  Ultra-low-power Arm® Cortex®-M33 MCUTrustZone®FPU,240 DMIPS, up to 512 KB flash memory, 274 KB SRAM
PDF  278 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U535NET3QTR 데이터시트(HTML) 210 Page - STMicroelectronics

Back Button STM32U535NET3QTR Datasheet HTML 206Page - STMicroelectronics STM32U535NET3QTR Datasheet HTML 207Page - STMicroelectronics STM32U535NET3QTR Datasheet HTML 208Page - STMicroelectronics STM32U535NET3QTR Datasheet HTML 209Page - STMicroelectronics STM32U535NET3QTR Datasheet HTML 210Page - STMicroelectronics STM32U535NET3QTR Datasheet HTML 211Page - STMicroelectronics STM32U535NET3QTR Datasheet HTML 212Page - STMicroelectronics STM32U535NET3QTR Datasheet HTML 213Page - STMicroelectronics STM32U535NET3QTR Datasheet HTML 214Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 210 / 278 page
background image
Electrical characteristics
STM32U535xx
210/278
DS14217 Rev 1
Figure 35. Output AC characteristics definition
5.3.15
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized
in Table 32.
Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.
T
10%
50%
90%
10%
50%
90%
r(IO)out
t
f(IO)out
t
Table 98. NRST pin characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST input low-level voltage
-
-
-
0.3 x VDDIOx
V
VIH(NRST)
NRST input high-level voltage
-
0.7 x VDDIOx
--
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
-
-
200
-
mV
RPU
Weak pull-up equivalent resistor(2)
VIN = VSS
30
40
50
kΩ
tF(NRST)
NRST input filtered pulse
-
-
-
50
ns
tNF(NRST)
NRST input not-filtered pulse
1.71 V ≤ VDD ≤ 3.6 V
330
-
-
1.58 V ≤ VDD ≤ 3.6 V
1000
-
-
1.
Specified by design. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order)
.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com