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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32U535NET3QTR 데이터시트(PDF) 237 Page - STMicroelectronics |
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STM32U535NET3QTR 데이터시트(HTML) 237 Page - STMicroelectronics |
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237 / 278 page  DS14217 Rev 1 237/278 STM32U535xx Electrical characteristics 253 Figure 46. ADF timing diagram MSv69124V1 ADF_SDIx (I) ADF_CCK (I/O) tSUCCKI tSUCCKO tSUCCKOLF fCCKI, fCCKO, fCCKOLF tLCCKI, tLCCKO, tLCCKOLF tHDCCKI tHDCCKO tHDCCKOLF tHCCKI, tHCCKO, tHCCKOLF tSUCCKI tSUCCKO tSUCCKOLF tHDCCKI tHDCCKO tHDCCKOLF Table 117. MDF characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fCKI Input clock frequency via MDF_CKIx pin, in SLAVE SPI mode 1.71 ≤ VDD ≤ 3.6 V -- 25 MHz fCCKI Input clock frequency via MDF_CCK[1:0] pin, in SLAVE SPI mode -- 25 fCCKO Output clock frequency in MASTER SPI mode -- 25 fCCKOLF Output clock frequency in LF_MASTER SPI mode -- 5 fSYMB Input symbol rate in Manchester mode -- 20 tHCKI tLCKI MDF_CKIx input clock high and low time In SLAVE SPI mode 2 × Tmdf_proc_ck(2) -- ns tHCCKI tLCCKI MDF_CCK[1:0] input clock high and low time In SLAVE SPI mode 2 × Tmdf_proc_ck -- tHCCKO tLCCKO MDF_CCK[1:0] output clock high and low time In MASTER SPI mode 2 × Tmdf_proc_ck -- tHCCKOLF tLCCKOLF MDF_CCK[1:0] output clock high and low time In LF_MASTER SPI mode Tmdf_proc_ck - - |
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