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STM32U535NET3QTR 데이터시트(PDF) 245 Page - STMicroelectronics

부품명 STM32U535NET3QTR
상세설명  Ultra-low-power Arm® Cortex®-M33 MCUTrustZone®FPU,240 DMIPS, up to 512 KB flash memory, 274 KB SRAM
PDF  278 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STM32U535NET3QTR 데이터시트(HTML) 245 Page - STMicroelectronics

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DS14217 Rev 1
245/278
STM32U535xx
Electrical characteristics
253
Figure 51. USART timing diagram in master mode
Table 126. USART characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fCK
USART clock
frequency
Master mode, 1.71 V ≤ VDDIOX ≤ 3.6 V
-
-
20
MHz
Slave receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V
-
-
53
Slave transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V
-
-
28.5
Slave transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V
-
-
32
tsu(NSS)
NSS setup
time
Slave mode
Tker(2) + 2
-
-
ns
th(NSS) NSS hold time Slave mode
2
-
-
tw(CKH)
tw(CKL)
CK high and
low time
Master mode
1/fCK / 2 - 1 1/fCK / 2 1/fCK / 2 + 1
tsu(RX)
Data input
setup time
Master mode
14
-
-
Slave mode
1
-
-
th(RX) Data input
hold time
Master mode
4
-
-
th(RX)
Slave mode
1
-
-
tv(TX)
Data output
valid time
Slave mode, 2.7 V ≤ VDD ≤ 3.6 V
-
11
17.5
Slave mode, 1.71 V ≤ VDD ≤ 3.6 V
-
11
15.5
tv(TX)
Master mode
-
2.5
6.5
th(TX)
Data output
hold time
Slave mode
8.5
-
-
th(TX)
Master mode
2
-
-
1. Evaluated by characterization. Not tested in production.
2. Tker is the usart_ker_ck_pres clock period.
MSv65386V4
CPHA = 0
TX
OUTPUT
RX
INPUT
CPHA = 0
LSB OUT
LSB IN
CPOL = 0
CPOL = 1
BIT1 OUT
1/fCK
tw(CKH)
tw(CKL)
th(RX)
CPHA = 1
CPHA = 1
CPOL = 0
CPOL = 1
tsu(RX)
tv(TX)
th(TX)
MSB IN
BIT6 IN
MSB OUT



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