ST25R3920 datasheet(45/152 Pages) STMICROELECTRONICS

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DS13261 Rev 9

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ST25R3920

Application information

151

FIFO water level and FIFO status registers, FIFO reset

The ST25R3920 features a 512 byte FIFO. The control logic shifts the data during

transmission, which was previously loaded by the external microcontroller to the framing

block and further to the transmitter. During reception, the demodulated data is stored in the

FIFO and the external microcontroller can receive data at a later moment.

The FIFO status register 2 also contains two bits that indicate that the FIFO was not

correctly served during TX/RX process (FIFO overflow and FIFO underflow).

A FIFO overflow is set when too many data are written into the FIFO. When this bit is set

during RX the external controller did not react on time on the water level IRQ and more than

512 bytes were written into the FIFO (including received CRC bytes). Consequently, the

received data is corrupted. When an overflow happens during TX, it means that the

controller has written more data than the FIFO size. The data to be transmitted is corrupted.

A FIFO underflow is set when data were read from an empty FIFO. When this bit is set

during RX the external controller read more data than was actually received. When an

underflow happens during TX, it means that the controller has failed to provide the quantity

of data defined in the number of transmitted bytes registers on time.

FIFO pointers and FIFO status are reset at the start of each data reception (at I_rxs). They

are also reset at Power-up and at commands Set Default and Clear FIFO. Reading out data

from empty/cleared fifo shows data = 0.

MCU_CLK

The pin MCU_CLK can be used as clock source for the external microcontroller. Depending

on the operation mode either a low frequency clock (32 kHz) from the RC oscillator or the

clock signal derived from crystal oscillator is available on pin MCU_CLK. The MCU_CLK

output pin is controlled by bits out_c<1:0> and lf_clk_off in the IO configuration register 1.

Bits out_c<1:0> enable the use of pin MCU_CLK as clock source and define the division

when the crystal oscillator is running (13.56, 6.78 and 3.39 MHz are available). Bit lf_clk_off

controls the use of low frequency clock (32 kHz) when the crystal oscillator is not running.

By default configuration, which is defined at power-up, the 3.39 MHz clock is selected and

the low frequency clock is enabled.

If the Transparent mode (see Section 4.4.13) is used the use of MCU_CLK is mandatory

since a clock synchronous with the field carrier frequency is needed to implement receive

and transmit framing in the external controller. The use of MCU_CLK is recommended also

when the internal framing is used. Using MCU_CLK as the microcontroller clock source

generates noise, synchronous with the reader carrier frequency and therefore filtered out by

the receiver, while using some other incoherent clock source can produce noise that

perturbs the reception. Use of MCU_CLK is also better for EMC compliance.

4.3.2

Communication interface selection

The active communication interface is selected via the I2C_EN pin. If this pin is pulled to

GND, the ST25R3920 operates in SPI mode. If this pin is pulled to VDD_D, the ST25R3920

operate in I2C mode.

4.3.3

Serial peripheral interface (SPI)

The ST25R3920 has a standard serial peripheral interface with clock polarity of 0, a clock

phase of 1, and an active low slave select signal. Communication starts with the MCU

pulling BSS low. The MOSI pin is samples on the falling edge of SCLK, and the state of the

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