ST25R3920 datasheet(47/152 Pages) STMICROELECTRONICS

47 / 152 page

DS13261 Rev 9

47/152

ST25R3920

Application information

151

Writing data to addressable registers (Write mode)

Figure 11 and Figure 12 show cases of writing, respectively, a single byte and multiple bytes

with auto-incrementing address. After the SPI operation mode bits, the address of register to

be written is provided. Then one or more data bytes are transferred from the SPI, always

MSB to LSB. The data byte is written in register on falling edge of its last clock. If the register

on the defined address does not exist or it is a read only register no write is performed.

Table 9. SPI operation modes

Mode

Pattern (communication bits)

Related data

Mode

Trailer

M1 M0 C5 C4 C3 C2 C1 C0

A0 Data byte (or more bytes in case of

auto-incrementing)

FIFO load

10000

000

One or more bytes of FIFO data

PT_memory load

A-config

10100

000

Passive target memory, locations from 0 on.

PT_memory load

F-config

10101

000

Passive target memory, locations from 15 on.

PT_memory load

TSN data

10101

100

Passive target memory, locations from 36 on.

The additional address allows reload of the

TSN random numbers without rewriting the

whole PT_memory

PT_memory read

10111

111

Passive target memory, locations from 0 on.

A 0 byte is presented to the passive target

memory to support reading at all SPI speeds.

FIFO read

One or more bytes of FIFO data

Direct command

C5 C4C3 C2C1C0

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