LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK

3

Rev C 1/5/15

85408 DATA SHEET

Table 3B. Clock Input Function Table

NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.

Inputs

Outputs

Input to Output Mode

Polarity

CLK

nCLK

Q[0:7]

nQ[0:7]

0

1

LOW

HIGH

Differential to Differential

Non-Inverting

1

0

HIGH

LOW

Differential to Differential

Non-Inverting

0

Biased; NOTE 1

LOW

HIGH

Single-Ended to Differential

Non-Inverting

1

Biased; NOTE 1

HIGH

LOW

Single-Ended to Differential

Non-Inverting

Biased; NOTE 1

0

HIGH

LOW

Single-Ended to Differential

Inverting

Biased; NOTE 1

1

LOW

HIGH

Single-Ended to Differential

Inverting