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85408BGLF 데이터시트(PDF) 1 Page - Renesas Technology Corp

부품명 85408BGLF
상세설명  Low Skew, 1-to-8, Differential-to-LVDS Clock
PDF  17 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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DATA SHEET
Low Skew, 1-to-8, Differential-to-LVDS
Clock
85408
85408 Rev C 1/5/15
1
©2015 Integrated Device Technology, Inc.
General Description
The 85408 is a low skew, high performance 1-to-8
Differential-to-LVDS Clock Distribution Chip. The 85408 CLK, nCLK
pair can accept most differential input levels and translates them to
3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling
(LVDS), the 85408 provides a low power, low noise, low skew,
point-to-point solution for distributing LVDS clock signals.
Guaranteed output and part-to-part skew specifications make the
85408 ideal for those applications demanding well defined
performance and repeatability.
Features
• Eight differential LVDS output pairs
• CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 700MHz
• Translates any differential input signal (LVPECL, LVHSTL, SSTL,
HCSL) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS with resistor
bias on nCLK input
• Output skew: 50ps (maximum)
• Part-to-part skew: 550ps (maximum)
• Propagation delay: 2.4ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
Q7
nQ7
GND
OE
VDD
VDD
GND
VDD
CLK
nCLK
Q0
nQ0
CLK
nCLK
OE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Pin Assignment
85408
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
Block Diagram


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