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S12SCIV3/D 데이터시트(PDF) 2 Page - NXP Semiconductors |
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S12SCIV3/D 데이터시트(HTML) 2 Page - NXP Semiconductors |
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2 / 98 page ![]() DOCUMENT NUMBER MC9S12KG128 Revision History Version Number Revision Date Author Description of Changes 01.00 16.JUL.02 Roberto Frontera Original Version 01,01 22 NOV 02 Daniel Yu Change load cap value on VDD and VDDPLL. Correct expanded bus timing from 20MHz to 25 MHz Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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