HC05RC17GRSSLASHD datasheet(11/128 Pages) NXP

11 / 128 page

MC68HC05RC17 — Rev. 2.0

General Release Specification

List of Figures

General Release Specification — MC68HC05RC17

List of Figures

Figure

Title

Page

1-1

MC68HC05RC17 Block Diagram . . . . . . . . . . . . . . . . . . . . .17

1-2

28-Pin SOIC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

1-3

28-Pin PDIP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

1-4

Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2-1

MC68HC05RC17 Memory Map . . . . . . . . . . . . . . . . . . . . . .28

2-2

I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3-1

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3-2

Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4-1

Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .42

4-2

IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .43

5-1

Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

5-2

Reset and POR Timing Diagram . . . . . . . . . . . . . . . . . . . . .49

5-3

COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . .53

6-1

Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .56

6-2

Stop/Wait Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

7-1

Port B Pullup Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7-2

I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

8-1

Core Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .64

8-2

Core Timer Control and Status Register (CTCSR) . . . . . . .65

8-3

Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . .67

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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