HC05RC17GRSSLASHD datasheet(116/128 Pages) NXP

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Electrical Speciﬁcations

General Release Specification

MC68HC05RC17 — Rev. 2.0

Electrical Specifications

12.8 DC Electrical Characteristics (2.2 Vdc)

Characteristic

Symbol

Min

Typ

Max

Unit

Output Voltage

ILoad = 10.0 µA

ILoad = –10.0 µA

VOL

VOH

—

VDD –0.1

—

0.1

—

Output High Voltage

(ILoad –0.6 mA) Port A, Port B, Port C (1–7)

(ILoad –2.5 mA) IRO

(ILoad –1.2 mA) Port C (Bit 0)

VOH

VDD –0.3

VDD –0.7

VDD –0.3

VDD –0.1

—

Output Low Voltage

(ILoad = 1.0 mA) Port A, Port B, Port C (1–7)

(ILoad = 8.0 mA) IRO

(ILoad = 7.0 mA) Port C (Bit 0)

VOL

—

0.1

0.3

0.8

0.3

Input High Voltage

Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1

VIH

0.7xVDD

—VDD

Input Low Voltage

Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1

VIL

VSS

—

0.4 x VDD

Supply Current (see Notes)

Run (fOP = 1.0 MHz)

Wait with PLL Enabled (fOP = 1.0 MHz)

Wait with PLL Disabled (fOP = 16.384 kHz)

Stop

25 oC

0 oC to +70 oC

IDD

—

0.5

0.2

21.0

0.1

1.0

0.8

40.0

1.0

4.0

µA

I/O Ports Hi-Z Leakage Current

Port A, Port B, Port C

IOZ

–4

—

µA

Input Current

RESET, LPRST, IRQ, OSC1

PB0–PB7 with Pullups Enabled (VIN = 0.4 x VDD)

PB0–PB7 with Pullups Enabled (VIN = 0.7 x VDD)

IIn

–0.4

–25

–15

—

–79

–35

0.4

–105

–65

µA

Capacitance

Ports (as Input or Output)

RESET, LPRST, IRQ

COut

CINT

—

NOTES:

1. VDD = 2.2 Vdc ± 10%, VSS = 0 Vdc, TA = 0 °C to +70 °C, unless otherwise noted

2. All values shown reflect average measurements.

3. Typical values at midpoint of voltage range, 25 oC only

4. All current measurements represent the summation of current through VDD and VDDSYN supply pins.

5. To minimize current consumption in wait mode, disable the PLL before executing the WAIT instruction. Internal bus

speed will be fosc of crystal ÷ 2.

6. Wait IDD: only core timer active

7. Run (with PLL enabled) IDD, wait IDD (with PLL enabled): Measured using external square wave clock source

(fOSC = 2.0 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait

IDD (with PLL disabled): Measured using external square wave clock source (fosc = 33 kHz).

8. Wait, stop IDD: Port A and port C configured as inputs, port B configured as outputs, VIL = 0.2 V, VIH = VDD –0.2 V

9. Stop IDD is measured with OSC1 = VSS.

10. Wait IDD is affected linearly by the OSC2 capacitance.

11. Pullups are designed to be capable of pulling to VIH within 25 µs for a 100 pF, 4-kΩ load.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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