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CEU6196 데이터시트(PDF) 4 Page - CET-MOS Technology Corp. |
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CEU6196 데이터시트(HTML) 4 Page - CET-MOS Technology Corp. |
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4 / 5 page ![]() CED6196/CEU6196 4 Qg, Total Gate Charge (nC) Figure 7. Gate Charge VDS, Drain-Source Voltage (V) Figure 8. Maximum Safe Operating Area Figure 10. Switching Test Circuit Figure 11. Switching Waveforms t V V t t d(on) OUT IN on r 10% td(off) 90% 10% 10% 50% 50% 90% toff tf 90% PULSE WIDTH INVERTED VDD R D V V R S V G GS IN GEN OUT L Tj, Junction Temperature ( C) Figure 9. Breakdown Voltage Variation VS Temperature 1.3 1.2 1.1 1 0.9 0.8 -50 0 50 100 150 10 3 10 2 10 1 10 0 10 -1 10 3 10 2 10 1 10 0 10 -1 RDS(ON)Limit Single Pulse TC=25 C TJ=150 C 10ms 1ms 100us DC 5 4 3 2 1 0 0 3 6 12 15 VDS=48V ID=20A 9 |
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