HC705C9AGRSSLASHD datasheet(143/157 Pages) NXP

143 / 157 page

General Release Specification

Serial Peripheral Interface Timing

MC68HC705C9A — Rev. 2.0

Electrical Specifications

Figure 12-9. SPI Master Timing Diagram

NOTE

NOTE:

SS pin of master held high.

MSB IN

(INPUT)

SCK (CPOL = 0)

(OUTPUT)

SCK (CPOL = 1)

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

NOTE

BIT 6–1

LSB IN

MASTER MSB OUT

BIT 6–1

MASTER LSB OUT

10 (ref)

11 (ref)

NOTE

NOTE:

SS pin of master held high.

MSB IN

(INPUT)

SCK (CPOL = 0)

(OUTPUT)

SCK (CPOL = 1)

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

NOTE

BIT 6–1

LSB IN

MASTER MSB OUT

BIT 6–1

MASTER LSB OUT

10 (ref)

a) SPI Master Timing (CPHA = 0)

b) SPI Master Timing (CPHA = 1)

This first clock edge is generated internally, but is not seen at the SCK pin.

This last clock edge is generated internally, but is not seen at the SCK pin.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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