APR9SLASHD datasheet(49/101 Pages) NXP

49 / 101 page

DSP56001A

External Bus Synchronous Timing

MOTOROLA

DSP56001A/D, Rev. 1

2-31

Note:

AC timing specifications which are referenced to a device input signal are measured in

production with respect to the 50% point of the respective input signal’s transition.

WS are wait state values specified in the BCR.

Clk Low transition to data-out invalid (specification # T146) and Clk Low transition to address

invalid (specification # T149) indicate the time after which data/address are no longer

guaranteed to be valid.

Timings are given from Clk midpoint to VOL or VOH of the corresponding signal(s).

Figure 2-23 Synchronous Bus Timing

Table 2-14

External Bus Synchronous Timing (Continued)

Num

Characteristics

27 MHz

33 MHz

Unit

Min

Max

Min

Max

Note:

During Read-Modify-Write Instructions, the address lines do not change states.

Data In

Data Out

CKOUT

A0–A15,

DS, PS,

X/Y

D0–D23

140

143

144

149

141

142

147

148

145

146

AA0395

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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