NV021 Data Sheet

©2016 Integrated Device Technology, Inc

Revision B January 26, 2016

8

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the NV021.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the NV021 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V

CC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)

MAX = VCC_MAX * IEE_MAX = 3.465V * 90mA = 311.85mW

• Power (outputs)

MAX = 30mW/Loaded Output pair

Total Power

_MAX (3.465V, with all outputs switching) = 311.85mW + 30mW = 341.85mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of

the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj =

θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance

θJA must be used. Assuming

a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 6A

below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.342W * 103.3°C/W = 120.3°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

TABLE 6A. THERMAL RESISTANCE

θJA FOR 8-PIN SOIC, FORCED CONVECTION

θJA by Velocity (Linear Feet per Minute)

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

153.3°C/W

128.5°C/W

115.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

112.7°C/W

103.3°C/W

97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 6B. THERMAL RESISTANCE

θJA FOR 8-PIN TSSOP, FORCED CONVECTION

θJA by Velocity (Meters per Second)

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

101.7°C/W

90.5°C/W

89.8°C/W