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PowerPC 602 RISC Microprocessor Hardware Specifications

1.7 System Design Information

This section provides electrical and thermal design recommendations for successful application of the 602.

1.7.1 PLL Configuration

The 602 has an internal programmable phased-lock loop (PLL). The PLL is programmed using the

PLL_CFG0–PLL_CFG3 pins. The PLL contains a voltage controlled oscillator (VCO) which is locked to

the incoming SYSCLK. The VCO is divided down to the CPU frequency (internal) and to the bus frequency

(SYSCLK). The PLL_CFG0–PLL_CFG3 pins are used to determine these frequency divisions. The 602 has

two bus modes (CPU/bus ratio), 2:1 and 3:1. The 602 also has two VCO divider ratios (VCO/CPU),

÷2 and

÷4.

In a system application, the bus frequency and bus mode is selected based on system requirements (for

example, 33 MHz, 2:1) and then the VCO divider is selected such that the VCO frequency is within the

typical lock range identified in Table 6 (for example, 66 MHz CPU,

÷4 such that VCO = 264 MHz).

The first two PLL_CFG pins, PLL_CFG0 and PLL_CFG1, determine the bus mode while the second two

pins, PLL_CFG2 and PLL_CFG3, determine the VCO divider ratio as shown in Table 11.

1.7.2 PLL Power Supply Filtering

The AVdd power signal is provided on the 602 to supply power to the clock generation phased-lock loop.

To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using

a circuit similar to the one shown in Figure 12. The circuit should be placed as close as possible to the AVdd

pin to ensure it filters out as much noise as possible.

Figure 12. PLL Power Supply Filter Circuit

Table 11. PLL Configuration

PLL_CFG0–PLL_CFG3 Setting

Bus Mode

VCO Divider

0100

2:1

÷2

0101

2:1

÷4

1000

3:1

÷2

1001

3:1

÷4

Note: It is important that the VCO frequency be selected such that it

falls within the typical VCO lock range identified in Table 6.

Vdd

AVdd

10 Ohms

10 uF

0

.1 uF

GND

Freescale Semiconductor, Inc.

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