PowerPC 602 RISC Microprocessor Hardware Specifications

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1.3.2.3 Output AC Specifications

Table 8 provides the output AC timing specifications for the 602.

Table 8. Output AC Timing Specifications

Vdd = 3.3

± 10% V dc, GND = 0 V dc, CL = 50 pF, 0 ≤ TJ ≤ 105 °C

Num

Characteristic

33.33 MHz Bus Clock/

66.67 MHz CPU Clock

40 MHz Bus Clock/

80 MHz CPUClock

Unit

Notes

Min

Max

Min

Max

12

SYSCLK to output driven (output enable

time)(AD0–AD63, TS, BB, BR, ARTRY)

1.0

—

1.0

—

ns

1,3

13

SYSCLK to output valid

(all outputs)

—

17

—

17

ns

1

14

SYSCLK to output invalid (output hold)

(AD0–AD63), TS, BB, BR, ARTRY)

4

—

4

—

ns

1

15

SYSCLK to output high impedance

(AD0–AD63, TS, BB, BR, ARTRY)

—

18

—

18

ns

1,2

16

SYSCLK to output driven (output enable

time) (RESETO, QREQ, CKSTP_OUT,

TDO)

1.0

—

1.0

—

ns

1,2,3

17

SYSCLK to output invalid (output hold)

(RESETO, QREQ, CKSTP_OUT)

1.0

—

1.0

—

ns

1,2

18

SYSCLK to output high impedance

(RESETO, QREQ, CKSTP_OUT)

—

18

—

18

ns

1,2

Notes:

1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to 1.4 V. Both input

and output timings are measured at the pin.

2. All maximum timing specifications assume CL = 50 pF.

3. These values are guaranteed by design and are not tested.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com