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SLG46867MTR 데이터시트(PDF) 49 Page - Renesas Technology Corp |
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SLG46867MTR 데이터시트(HTML) 49 Page - Renesas Technology Corp |
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49 / 209 page ![]() Datasheet 28-Feb-2023 CFR0011-120-00 Revision 3.21 Page 49 of 208 © 2023 Renesas Electronics Corporation SLG46867 GreenPAK Programmable Mixed-Signal Matrix with Dual 44 m Ω/2 A P-FET Figure 16: 2-bit LUT1 or DFF1 Figure 17: 2-bit LUT2 or DFF2 DFF1 CLK D 2-bit LUT1 OUT IN0 IN1 To Connection Matrix Input [2] 4-bits NVM From Connection Matrix Output [3] 1-bit NVM registers [1503:1500] register [1489] From Connection Matrix Output [2] Q/nQ register [1503] DFF or LATCH Select register [1502] Output Select (Q or nQ) register [1501] DFF Initial Polarity Se- lect LUT Truth Table DFF/Latch Registers S0 S1 S0 S1 S0 S1 0: 2-bit LUT1 IN1 1: DFF1 Data 0: 2-bit LUT1 Out 1: DFF1 Out 0: 2-bit LUT1 IN0 1: DFF1 CLK DFF2 CLK D 2-bit LUT2 OUT IN0 IN1 To Connection Matrix Input [3] 4-bits NVM From Connection Matrix Output [5] 1-bit NVM registers [1507:1504] register [1490] From Connection Matrix Output [4] Q/nQ register [1507] DFF or LATCH Select register [1506] Output Select (Q or nQ) register [1505] DFF Initial Polarity Se- lect LUT Truth Table DFF/Latch Registers S0 S1 S0 S1 S0 S1 0: 2-bit LUT2 IN1 1: DFF2 Data 0: 2-bit LUT2 Out 1: DFF2 Out 0: 2-bit LUT2 IN0 1: DFF2 CLK |
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