Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

16

Figure 11 shows the reset timing diagram.

Figure 11. Reset Timing Diagram

22

DMA Requests Rate

• Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1

6

× TC

—

30.0

ns

• Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1

7

× TC

—

35.0

ns

• Timer, Timer_1

2

× TC

—

10.0

ns

•IRQ, NMI (edge trigger)

3

× TC

—

15.0

ns

Notes:

1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply

to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using

fast interrupts. Long interrupts are recommended when using Level-sensitive mode.

2. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined

by the OMR Bit 6 settings.

For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL

to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200

μs.

3. Periodically sampled and not 100% tested.

4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and

valid. When VDD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the

device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should

minimize this state to the shortest possible duration.

Table 7. Reset, Stop, Mode Select, and Interrupt Timing Parameters

No.

Characteristics

Expression

Min

Max

Unit

VIH

RESET

All Pins

10

11

13

Reset Value