STR750F datasheet(64/73 Pages) STMICROELECTRONICS

64 / 73 page

Electrical parameters

STR750F

64/71

3.3.12

10-bit ADC characteristics

Subject to general operating conditions for VDDA_ADC, fPCLK, and TA unless otherwise

specified.

Table 40.

10-bit ADC characteristics

Symbol

Parameter

Conditions

Min

Typ(1)

Unless otherwise specified, typical data are based on TA=25°C. They are given only as design guidelines

and are not tested.

Max

Unit

fADC

ADC clock frequency

0.4

MHz

VAIN

Conversion voltage range

VSSA_ADC

VDDA_ADC

RAIN

External input impedance

TBD(2)(3)(4)

CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus

the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this,

fADC should be reduced.

Depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and reduced to

allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 8 MHz.

Calibration is needed once after each power-up.

Ω

CAIN

External capacitor on analog

input

Ilkg

Induced input leakage current

+400 µA injected

on any pin

µA

-400 µA injected

on any pin

except specific

adjacent pins in

Table 41

µA

-400µA injected

on specific

adjacent pins in

Table 41

µA

CADC

Internal sample and hold

capacitor

3.5

tCAL

Calibration Time

fCK_ADC=8 MHz

725.25

µs

5802

1/fADC

tCONV

Total Conversion time

(including sampling time)

fCK_ADC=8 MHz

3.75

µs

30 (11 for sampling + 19 for

Successive Approximation)

1/fADC

IADC

Sunk on

VDDA_ADC

3.7

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