PCF5271CVM100 datasheet(51/56 Pages) FREESCALE

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Preliminary Electrical Characteristics

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

Freescale Semiconductor

The values in Table 42 correspond to Figure 19.

Figure 19. QSPI Timing

8.13 JTAG and Boundary Scan Timing

Table 43. JTAG and Boundary Scan Timing

Num

Characteristics1

NOTES:

JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

Symbol

Min

Max

Unit

TCLK Frequency of Operation

fJCYC

1/4

fsys/2

TCLK Cycle Period

tJCYC

tCYC

TCLK Clock Pulse Width

tJCW

TCLK Rise and Fall Times

tJCRF

Boundary Scan Input Data Setup Time to TCLK Rise

tBSDST

Boundary Scan Input Data Hold Time after TCLK Rise

tBSDHT

TCLK Low to Boundary Scan Output Data Valid

tBSDV

033

TCLK Low to Boundary Scan Output High Z

tBSDZ

033

TMS, TDI Input Data Setup Time to TCLK Rise

tTAPBST

J10

TMS, TDI Input Data Hold Time after TCLK Rise

tTAPBHT

J11

TCLK Low to TDO Data Valid

tTDODV

026

J12

TCLK Low to TDO High Z

tTDODZ

J13

TRST Assert Time

tTRSTAT

100

J14

TRST Setup Time (Negation) to TCLK High

tTRSTST

QSPI_CS[1:0]

QSPI_CLK

QSPI_DOUT

QS5

QS1

QSPI_DIN

QS3

QS4

QS2

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