AM29BDS128H datasheet(82/89 Pages) SPANSION

부품명	AM29BDS128H

상세설명	128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

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Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A TA

SH EE T

AC CHARACTERISTICS)

Notes:

1. RDY active with data (A18 = 0 in the Configuration Register).

2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).

3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing

a bank in the process of performing an erase or program.

4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency at

the boundary crossing.

Figure 46.

Latency with Boundary Crossing

CLK

Address (hex)

C60

C61

C62

C63

C64

C65

C66

C67

D60

D61

D62

D63

D64

D65

D66

D67

(stays high)

AVD#

RDY(1)

Data

Address boundary occurs every 64 words, beginning at address

00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

latency

RDY(2)

latency

tRACC

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