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GLT6400L08LL-85ST 데이터시트(PDF) 5 Page - List of Unclassifed Manufacturers |
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GLT6400L08LL-85ST 데이터시트(HTML) 5 Page - List of Unclassifed Manufacturers |
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5 / 10 page ![]() G -LINK GLT6400L08 Ultra Low Power 512k x 8 CMOS SRAM Feb 2001(Rev. 1.1) G-Link Technology Corporation 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F No. 24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 5 - Data Retention Waveform Data Retention Mode Vcc CE VDR VDR >= 1.0V tR tCDR 2.7V 2.7V VIH VIH AC Test Conditions AC Test Loads and Waveforms CL* TTL Output Load Condition *Including Scope and Jig Capacitance CL = 30pf + 1TTL Load Read Cycle (3,9)( 70ns Vcc=3V to 3.6V , 85ns Vcc=2.7V to 3.3V ) 70 85 Unit Note Parameter Symbol Min Max Min Max Read Cycle Time tRC 70 85 ns Address Access Time tAA 70 85 ns Chip Enable Access Time tACE 70 85 ns Output Enable Access Time tOE 40 40 ns Output Hold from address Change tOH 10 10 ns Chip Enable to Output in Low-Z tCLZ 10 10 ns 4,5 Chip Disable to Output in High-Z tCHZ 25 35 ns 4,5 Output Enable to Output in Low-Z tOLZ 5 5 ns 4,5 Output Disable to Output in High-Z tOHZ 25 30 ns 4,5 Power-Up Time tPU 0 0 ns 5 Power-Down Time tPD 70 85 ns 5 Input Pulse Levels 0.4V to 2.4V Input Rise and Fall Time Input and Output Timing Reference Level 5 ns 1.4V |
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