GLT6400L08LL-85ST datasheet(6/10 Pages) ETC

6 / 10 page

G -LINK

GLT6400L08

Ultra Low Power 512k x 8 CMOS SRAM

Feb 2001(Rev. 1.1)

G-Link Technology Corporation

2701 Northwestern Parkway

Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

6F No. 24-2, Industry E. RD. IV, Science Based

Industrial Park, Hsin Chu, Taiwan.

- 6 -

Timing Waveform of Read Cycle 1

(3,6,7,9) (Address Controlled)

DOUT

tAA

tOH

tRC

Data Valid

Address

Timing Waveform of Read Cycle 2

(5,6,8,9) ( CE1 Controlled)

tOE

tRC

Data Valid

CE1

tOHZ

tCHZ

tPD

50%

tOLZ

tACE

tCLZ

tPU

Supply Current

DOUT

ICC

ISB

Write Cycle

(3,11)( 70ns Vcc=3V to 3.6V , 85ns Vcc=2.7V to 3.3V )

Parameter

Symbol

Min

Max

Min

Max

Unit Note

Write Cycle Time

tWC

Chip Enable to Write End

tCW

Address Setup to Write End

tAW

Address Setup Time

tAS

Write Pulse Width

tWP

Write Recovering Time

tWR

Data Valid to Write End

tDW

Data Hold Time

tDH

Write Enable to Output in High-Z

tWZ

4,5

Output Active from Write End

tOW

4,5

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