NAND04GW3B2B datasheet(13/58 Pages) STMICROELECTRONICS

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NAND04GW3B2B, NAND08GW3B2A

Signal descriptions

13/58

Signal descriptions

See Figure 2: Logic Diagram, and Table 2: Signal Names, for a brief overview of the signals

connected to this device.

3.1

Inputs/Outputs (I/O0-I/O7)

Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read

operation or input a command or data during a Write operation. The inputs are latched on

the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or

the outputs are disabled.

3.2

Address Latch Enable (AL)

The Address Latch Enable activates the latching of the Address inputs in the Command

Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.

3.3

Command Latch Enable (CL)

The Command Latch Enable activates the latching of the Command inputs in the Command

Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.

3.4

Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and

sense amplifiers. When Chip Enable is low, VIL, the device is selected. If Chip Enable goes

high, vIH, while the device is busy, the device remains selected and does not go into standby

mode.

3.5

Read Enable (R)

The Read Enable pin, R, controls the sequential data output during Read operations. Data

is valid tRLQV after the falling edge of R. The falling edge of R also increments the internal

column address counter by one.

3.6

Power-Up Read Enable, Lock/Unlock Enable (PRL)

The Power-Up Read Enable, Lock/Unlock Enable input, PRL, is used to enable and disable

the lock mechanism. When PRL is High, VIH, the device is in Block Lock mode.

If the Power-Up Read Enable, Lock/Unlock Enable input is not required, the PRL pin should

be left unconnected (Not Connected) or connected to VSS.

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