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ICS841402I 데이터시트(PDF) 2 Page - Renesas Technology Corp

부품명 ICS841402I
상세설명  FemtoClock® Crystal-to-0.7V Differential HCSL Clock Generator
PDF  28 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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ICS841402I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-0.7V DIFFERENTIAL HCSL CLOCK GENERATOR
ICS841402DKI REVISION A NOVEMBER 7, 2012
2
©2012 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number
Name
Type
Description
1,
2
XTAL_IN,
XTAL_OUT
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input. (PLL reference.)
3
MR/nOE
Input
Pulldown
Master reset. LVCMOS/LVTTL interface levels. See Table 3D.
4, 14, 24, 29
VDD
Power
Core supply pins.
5, 6
Q0, nQ0
Output
Differential output pair. HCSL interface levels.
7, 8
Q1, nQ1
Output
Differential output pair. HCSL interface levels.
9, 19, 32
GND
Power
Power supply ground.
10, 11, 12,
13, 15, 16,
17, 18
nc
Unused
No connect.
20
OE_REFOUT
Input
Pulldown
Output enable pin. LVCMOS/LVTTL interface levels. See Table 3F.
21
REF_OUT
Output
Reference clock output. LVCMOS/LVTTL interface levels. In PCIe Gen 2
and Gen 3 applications, the REF_OUT output should be disabled.
22
F_SEL0
Input
Pulldown
Output frequency select pin. LVCMOS/LVTTL interface levels.
See Table 3B.
23
F_SEL1
Input
Pullup
Output frequency select pin. LVCMOS/LVTTL interface levels.
See Table 3B.
25
SSM
Input
Pulldown
Spread-spectrum selection. LVCMOS/LVTTL interface levels.
See Table 3A.
26
IREF
Output
0.7V current reference resistor output. A fixed precision resistor (475
)
from this pin to ground provides a reference current used for differential
current-mode Qx, nQx clock outputs.
27
BYPASS
Input
Pulldown
Selects PLL operation/PLL bypass operation. See Table 3C.
LVCMOS/LVTTL interface levels.
28
VDDA
Power
Analog supply pin.
30
REF_SEL
Input
Pulldown
Reference select. Selects the input reference source.
LVCMOS/LVTTL interface levels. See Table 3E.
31
REF_IN
Input
Pulldown
LVCMOS/LVTTL PLL reference clock input.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
k
RPULLUP
Input Pullup Resistor
51
k
ROUT
Output
Impedance
REF_OUT
27



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