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ICS93732 데이터시트(PDF) 1 Page - Renesas Technology Corp |
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ICS93732 데이터시트(HTML) 1 Page - Renesas Technology Corp |
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1 / 9 page ![]() ICS93732 0578J—06/20/08 Block Diagram Low Cost DDR Phase Lock Loop Zero Delay Buffer Pin Configuration Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz (DDR 533) •I 2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • CYCLE - CYCLE jitter (66MHz): <120ps • CYCLE - CYCLE jitter (>100MHz): <65ps • CYCLE - CYCLE jitter (>200MHz): <75ps • OUTPUT - OUTPUT skew: <100ps • DUTY CYCLE: 49.5% - 50.5% Functionality S T U P N IS T U P T U O e t a t S L L P D D V AT N I _ K L CT K L CC K L CT T U O _ B F V 5 . 2 ) m o n ( LL H L n o V 5 . 2 ) m o n ( HH L H n o FB_INT FB_INT CLK_INT CLK_INT SCLK SCLK SD SDA AT TA A Control Control Logic Logic FB_OUTT FB_OUTT DDRC0 DDRC0 PLL PLL DDRT0 DDRT0 DDRC1 DDRC1 DDRT1 DDRT1 DDRC2 DDRC2 DDRT2 DDRT2 DDRC3 DDRC3 DDRT3 DDRT3 DDRC4 DDRC4 DDRT4 DDRT4 DDRC5 DDRC5 DDRT5 DDRT5 DDRC0 DDRT0 DDRT1 DDRC1 DDRT3 DDRC3 DDRC4 DDRT4 DDRT2 DDRC2 VDD VDD VDD VDDA DDRC5 DDRT5 GND GND GND GND SCLK CLK_INT FB_OUTT FB_INT SDATA N/C N/C N/C 28-pin 209mil SSOP |
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