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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

Worst power draw for the 80KSW0005 is approximately 7W total. The condition is all ports @ 3.125G under 100% switch load at the max driving

strength and all trace function are enable.

13 I2C-Bus

The CPS-10Q is compliant with the I2C specification [1]. This specification provides all functional detail and electrical specifications associated with the

I2C bus. This includes signaling, addressing, arbitration, AC timing, DC specifications, and other details.

The device supports both master mode and slave mode, it’s selected by MM pin.

The I2C bus is comprised of Serial Data (SDA) and Serial Clock (SCL) pins. It can be used to attach a CPU or a configuration memory. The I2C inter-

face supports Fast/Standard (F/S) mode (400/ 100 kHz).

I2C master mode and slave mode

The CPS-10Q devices support both master mode and slave mode. It’s selected by MM static configuration pin. Refer to the below for signaling and

operation.

I2C Device Address

The device address for the CPS-10Q is fully pin-defined by 10 external pins while in slave mode. This provides full flexibility in defining the slave

address to avoid conflicting with other I2C devices on a given bus. The device can be operated as either a 10-bit addressable device or a 7-bit

addressable device based on another external pin, address select (ADS). If the ADS pin is tied to VDD, then the CPS-10Q operates as a 10-bit

addressable device and the device address will be defined as ID[9:0]. If the ADS pin is tied to GND, then the device operates as a 7-bit addressable

device with the device address defined by ID[6:0]. The addressing mode must be established at power-up and remain static throughout operation.

Dynamic changes will result in undetermined behavior.

All of the CPS-10Q’s registers are addressable through I2C. These registers are accessed via 22-bit addresses and 32-bit word boundaries though

standard reads and writes. These registers may also be accessed through the sRIO and JTAG interfaces.

Pin

I2C Address Bit (pin_addr)

ID0

0

ID1

1

ID2

2

ID3

3

ID4

4

ID5

5

ID6

6

ID7

7 (don’t care in 7-bit mode)

ID8

8 (don’t care in 7-bit mode)

ID9

9 (don’t care in 7-bit mode)

Table 11 I2C Static Address Selection Pin Configuration