CDP1802AC datasheet(12/27 Pages) RENESAS

12 / 27 page

CDP1802AC/3

FN1441 Rev 3.00

Page 12 of 27

October 17, 2008

FIGURE 10. DMA IN CYCLE TIMING WAVEFORMS

FIGURE 11. DMA OUT CYCLE TIMING WAVEFORMS

Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)

CLOCK

TPA

TPB

MACHINE

INSTRUCTION

DMA-IN

MRD

MWR

MEMORY

DATA BUS

CYCLE

OUTPUT

NOTE: USER GENERATED SIGNAL

MEMORY READ CYCLE

MEMORY READ, WRITE

MEMORY WRITE CYCLE

OR NON-MEMORY CYCLE

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

(NOTE)

VALID DATA FROM INPUT DEVICE

CYCLE n

FETCH (S0)

CYCLE (n+1)

EXECUTE (S1)

CYCLE (n+2)

DMA (S2)

VALID OUTPUT

345

234

CLOCK

TPA

TPB

MACHINE

CYCLE

INSTRUCTION

DMA OUT

MRD

MWR

MEMORY

OUTPUT

DATA

STROBE

(S2 ² TPB)

CYCLE n

CYCLE (n + 1)

CYCLE (n + 2)

DMA (S2)

EXECUTE (S1)

FETCH (S0)

VALID OUTPUT

VALID DATA FROM MEMORY

NOTE: USER GENERATED SIGNAL

MEMORY READ CYCLE

MEMORY READ, WRITE

MEMORY READ CYCLE

OR NON-MEMORY CYCLE

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

(NOTE)

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