CDP1802AC/3

FN1441 Rev 3.00

Page 25 of 27

October 17, 2008

Operating and Handling Considerations

Handling

All inputs and outputs of Intersil CMOS devices have a

network for electrostatic protection during handling.

Operating

OPERATING VOLTAGE

During operation near the maximum supply voltage limit care

should be taken to avoid or suppress power supply turn-on

and turn-off transients, power supply ripple, or ground noise;

any of these conditions must not cause VDD - VSS to exceed

the absolute maximum rating.

INPUT SIGNALS

To prevent damage to the input protection circuit, input

signals should never be greater than VDD nor less than VSS.

Input currents must not exceed 10mA even when the power

supply is off.

UNUSED INPUTS

A connection must be provided at every input terminal. All

unused input terminals must be connected to either VDD or

VSS, whichever is appropriate.

OUTPUT SHORT CIRCUITS

Shorting of outputs to VDD or VSS may damage CMOS

devices by exceeding the maximum device dissipation.

S1

F

8

LDl

MRP

 D; RP + 1  RP

MRP

RP

0

1

0

Fig. 6

9

ORl

MRP OR D

 D; RP + 1  RP

A

ANl

MRP AND D

 D; RP + 1  RP

B

XRl

MRP XOR D

 D; RP + 1  RP

C

ADl

MRP + D

 DF, D; RP + 1  RP

D

SDl

MRP - D

 DF, D; RP + 1  RP

F

SMl

D - MRP

 DF, D; RP +1  RP

E

SHL

MSB(D)

 DF; 0  LSB(D)

Float

RP

1

1

0

Fig. 4

S2

DMA IN

BUS

 MR0; R0 + 1  R0

Data from

I/O Device

R0

1

0

0

22, Fig. 10

DMAOUT

MR0

 BUS; R0 + 1  R0

MR0

R0

0

1

0

22, Fig. 11

S3

INTERRUPT

X, P

 T; 0  lE, 1  P;

2

 X

Float

RN

1

1

0

Fig. 12

S1

LOAD

IDLE (CLEAR, WAlT = 0)

M(R0 - 1)

R0 - 1

0

1

0

21, Fig. 6

NOTES:

17. lE = 1, TPA, TPB suppressed, state = S1.

18. BUS = 0 for entire cycle.

19. Next state always S1.

20. Wait for DMA or INTERRUPT.

21. Suppress TPA, wait for DMA.

22. IN REQUEST has priority over OUT REQUEST.

23. See “Timing Waveforms” beginning on page 7 and Figures 3 through 12 for “Machine Cyle Timing Waveforms beginning on page 9.

TABLE 5. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)

STATE

I

N

SYMBOL

OPERATION

DATA

BUS

MEMORY

ADDRESS

MRD

MWR

N

LINES

NOTES