000-005NT026-101

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SLG5NT026

Device Operation

In a typical application, de-asserting ON (low) turns off the external power N-FET. When ON is asserted (high), the device will

not begin driving the gate of the external power FET unless the voltage at the drain of the device is at or above 0.8 V

(e.g. VD ≥ 0.8). Gate voltage is not applied to the gate of the external power N-FET after DLY_t then the gate source (Vgs) voltage

is ramped up to 11.5 V above the source voltage VS at a slew rate determined by the internal slew rate control element internal

to the SLG5NT026. Monotonic rise of Vs is maintained even as ID increases dramatically after the load device turn on threshold

voltage is reached. After the source voltage has ramped up to its maximum steady state value, the Open Drain PG (Power Good)

signal is asserted. PG may be used as the ON control of a second SLG5NT026 thereby providing power on sequence control of

a number of switched power rails, or used in a ‘wired and’ with other PG signals to indicate all switched power rails are in a power

good condition.

If the ON signal has been asserted prior to the application of VCC, the device will begin turning on the external power FET after

VCC ramps up