전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

NB2304AI2DG 데이터시트(PDF) 7 Page - ON Semiconductor

부품명 NB2304AI2DG
상세설명  3.3 V Zero Delay Clock Buffer
PDF  10 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB2304AI2DG 데이터시트(HTML) 7 Page - ON Semiconductor

Back Button NB2304AI2DG Datasheet HTML 2Page - ON Semiconductor NB2304AI2DG Datasheet HTML 3Page - ON Semiconductor NB2304AI2DG Datasheet HTML 4Page - ON Semiconductor NB2304AI2DG Datasheet HTML 5Page - ON Semiconductor NB2304AI2DG Datasheet HTML 6Page - ON Semiconductor NB2304AI2DG Datasheet HTML 7Page - ON Semiconductor NB2304AI2DG Datasheet HTML 8Page - ON Semiconductor NB2304AI2DG Datasheet HTML 9Page - ON Semiconductor NB2304AI2DG Datasheet HTML 10Page - ON Semiconductor  
Zoom Inzoom in Zoom Outzoom out
 7 / 10 page
background image
NB2304A
http://onsemi.com
7
Zero Delay and Skew Control
For applications requiring zero input−output delay, all
outputs must be equally loaded.
Figure 3. REF Input to CLKA/CLKB Delay vs.
Difference in Loading between FBK Pin and
CLKA/CLKB Pins
1500
1000
500
0
−500
−1000
−1500
−30 −25 −20 −15 −10 −5
0
5
10
1520
2530
OUTPUT LOAD DIFFERENCE: FBK LOAD − CLKA/CLKB LOAD (pF)
To close the feedback loop of the NB2304A, the FBK pin
can be driven from any of the four available output pins. The
output driving the FBK pin will be driving a total load of
7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs)
can adjust the input output delay. This is shown in Figure 3.
For applications requiring zero input−output delay, all
outputs including the one providing feedback should be
equally loaded. If input−output delay adjustments are
required, use Figure 3 to calculate loading differences
between the feedback output and remaining outputs. For
zero output−output skew, be sure to load outputs equally.
SWITCHING WAVEFORMS
Figure 4. Duty Cycle Timing
1.4 V
1.4 V
1.4 V
t1
t2
Figure 5. All Outputs Rise/Fall Time
t3
OUTPUT
2.0 V
0.8 V
t4
2.0 V
0.8 V
3.3 V
0 V
1.4 V
1.4 V
t5
Figure 6. Output − Output Skew
OUTPUT
OUTPUT
t6
INPUT
OUTPUT
Figure 7. Input − Output Propagation Delay
VDD
2
VDD
2
Figure 8. Device − Device Skew
t7
FBK_Device 1
VDD
2
VDD
2
FBK_Device 2



Html Pages

1 2 3 4 5 6 7 8 9 10


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com