CS5501-SD datasheet(14/54 Pages) CIRRUS

14 / 54 page

The eighth output window time overlaps the time

in which the serial output port is to be updated. If

the CS is recognized as being low when it is

polled for the eighth window time, data will be

output as normal, but the serial port will not be

updated with new data until the next serial port

update time. Under these conditions, the serial

port will experience an update rate of only 2 kHz

(CLKIN = 4.096 MHz) instead of the normal

4 kHz serial port update rate.

Upon completion of transmission of all the data

bits, the SCLK and SDATA outputs will go to a

high impedance state even with CS held low. In

the event that CS is taken high before all data bits

are output, the SDATA and SCLK outputs will

Analog Time 1

Digital Time1

64/CLKIN

=1024/CLKIN

76/CLKIN

SCLK (o)

SDATA (o)

Hi-Z

Analog Time 0

Digital Time 0

(MSB)

(LSB)

64/CLKIN

Hi-Z

Note 1

CS Polled

DRDY (o)

CS (i)

Internal

Status

CS5501

SCLK (o)

SDATA (o)

Hi-Z

(MSB)

(LSB)

Hi-Z

CS5503

fout

Note: 1. There are 16 analog and digital settling periods per filter cycle (4 are shown). Data can be output in the

SSC mode in only 1 of the 8 digital time periods in each filter cycle.

Figure 4. Internal Timing

Hi-Z

SCLK (o)

SDATA (o)

DRDY (o)

CS (i)

CLKIN (i)

(MSB)

(LSB)

76 CLKIN cycles

B15*

B19**

B14*

B18**

CS5501

CS5503

Figure 5. Synchronous Self-Clocking (SSC) Mode Timing

CS5501/CS5503

DS31F2

CS5501-SD 데이터시트(PDF) 14 Page - Cirrus Logic

CS5501-SD 데이터시트(HTML) 14 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

데이터시트 다운로드

링크 URL