CS5501-SD datasheet(34/54 Pages) CIRRUS

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APPENDIX A: APPLICATIONS

Parallel Interface

Figures A1 and A2 show two serial-to-parallel

conversion circuits for interfacing the CS5501 in

its SSC mode to 16- and 8-bit systems respec-

tiv ely. Each circuit includes an optional

74HCT74 flip-flop to latch DRDY and generate

a level-sensitive interrupt.

Both circuits require that the parallel read process

be synchronized to the CS5501’s operation. That

is, the system must not try to enable the regis-

ters’ parallel output while they are accepting

serial data from the CS5501. The CS5501’s

DRDY falls just prior to serial data transmission

and returns high as the last bit shifts out. There-

fore, the DRDY pin can be polled for a rising

transition directly, or it can be latched as a level-

sensitive interrupt.

With the CS input tied low the CS5501 will shift

out every available sample (4kHz word rate with

a 4MHz master clock). Lower output rates (and

interrupt rates) can be generated by dividing

down the DRDY output and applying it to CS.

Totally asynchronous interfaces can be created

using a Shift Data control signal from the system

which enables the CS5501’s CS input and/or the

shift registers’ S1 inputs. The DRDY output can

then be used to disable serial data transmission

once an output word has been fully registered.

+5V

OE2 OE1

OE1

D10

D11

D12

D13

D14

D15

DRDY

(For polling)

MODE

SDATA

SCLK

DRDY

+5V

SET

RESET

INT

OE2

Only needed for

interrupt driven systems

CS5501

CS5503

Figure A1. 16-bit Parallel Interface

CS5501/CS5503

DS31F2

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