ADP3118 datasheet(3/16 Pages) AD

3 / 16 page

ADP3118

Rev. 0 | Page 3 of 16

SPECIFICATIONS1

VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

PWM INPUT

Input Voltage High

2.0

Input Voltage Low

0.8

Input Current

−1

µA

Hysteresis

250

OD INPUT

Input Voltage High

2.0

Input Voltage Low

0.8

Input Current

−1

µA

Hysteresis

250

Propagation Delay Times2

tpdlOD

See Figure 3

tpdhOD

See Figure 3

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current

BST − SW = 12 V

2.2

3.5

Ω

Output Resistance, Sinking Current

BST − SW = 12 V

1.0

2.5

Ω

Output Resistance, Unbiased

BST − SW = 0 V

kΩ

Transition Times

trDRVH

BST − SW = 12 V, CLOAD = 3 nF, see Figure 4

tfDRVH

BST − SW = 12 V, CLOAD = 3 nF, see Figure 4

Propagation Delay Times2

tpdhDRVH

BST − SW = 12 V, CLOAD = 3 nF, see Figure 4

tpdlDRVH

BST − SW = 12 V, CLOAD = 3 nF, see Figure 4

SW Pull-Down Resistance

SW to PGND

kΩ

LOW-SIDE DRIVER

Output Resistance, Sourcing Current

2.0

3.2

Ω

Output Resistance, Sinking Current

1.0

2.5

Ω

Output Resistance, Unbiased

VCC = PGND

kΩ

Transition Times

trDRVL

CLOAD = 3 nF, see Figure 4

tfDRVL

CLOAD = 3 nF, see Figure 4

Propagation Delay Times2

tpdhDRVL

CLOAD = 3 nF, see Figure 4

tpdlDRVL

CLOAD = 3 nF, see Figure 4

Timeout Delay

SW = 5 V

110

190

SW = PGND

150

SUPPLY

Supply Voltage Range

VCC

4.15

13.2

Supply Current

ISYS

BST = 12 V, IN = 0 V

UVLO Voltage

VCC rising

1.5

3.0

Hysteresis

350

1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.

2 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.

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