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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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VL6524 데이터시트(PDF) 27 Page - STMicroelectronics |
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VL6524 데이터시트(HTML) 27 Page - STMicroelectronics |
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27 / 70 page  VL6524/VS6524 Data synchronization methods 27/70 Figure 13. ITU656 frame structure with even codes The synchronization codes for odd and even frames are listed in Table 3 and Table 4. By default all frames output from the VL6524/VS6524 are EVEN. It is possible to set all frames to be ODD or to alternate between ODD and EVEN using the SyncCodeSetup register in the Output formatter control register bank. Table 3. ITU656 embedded synchronization code definition (even frames) Name Description 4-byte sequence SAV Line start - active FF 00 00 80 EAV Line end - active FF 00 00 9D SAV (blanking) Line start - blanking FF 00 00 AB EAV (blanking) Line end - blanking FF 00 00 B6 EAV SAV Frame of image data Line 1 Line 480 Frame blanking period 9D 80 EAV B6 SAV AB |
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